- Minimum of 5 years of combined ASIC/FPGA design and verification experience.
- Strong background in formal property verification (FPV), sequential equivalence checking (SEQ/SEC/SLEC), and formal methods.
- Proficiency in formal property languages (SVA), abstraction techniques, and commercial formal verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
- Extensive experience verifying complex designs, particularly those involving high-speed protocols like PCIe, SATA, USB, and AXI.
- Familiarity with verifying Hardware-Firmware interactions is highly desirable.
