We are currently seeking a highly skilled PCIe Express Gen4/5/6 Verification Engineer with expertise in the transport layer, data link layer, and PIPE interface, along with extensive experience in SystemVerilog (SV) and Universal Verification Methodology (UVM). If you have a minimum of 5 years of experience in this field and are passionate about ensuring the reliability and functionality of PCIe designs, we want to hear from you.

As a PCIe Express Verification Engineer, you will play a key role in verifying the functionality and compliance of PCIe Gen4/5/6 designs, particularly focusing on the transport layer, data link layer, and PIPE interface. Your responsibilities will include developing and executing verification plans, creating testbenches using SV/UVM methodologies, and debugging test failures. Additionally, you will collaborate closely with design and architecture teams to ensure that PCIe designs meet all specifications and requirements.

The ideal candidate will have a strong background in PCIe verification, including expertise in the transport layer, data link layer, and PIPE interface. Proficiency in SystemVerilog and UVM is essential, along with excellent debugging and problem-solving skills. Additionally, familiarity with industry-standard verification tools and methodologies is highly desirable.