Responsibilities:

• Engage in SoC specifications reviews and contribute to micro-architecture definitions.
• Execute front-end digital design and implementation – RTL coding, CDC, Lint, and synthesis.
• Formulate design constraints and collaborate to debug both functional and DFT test issues.
• Coordinate project activities and provide regular status updates.
• Enhance SoC design methodologies and verification quality.
• Collaborate with IP/Design Verification/Firmware/Software System/Production teams to address design and implementation issues in a timely manner.

Job Requirements

• Master’s and/or Bachelor’s degree in engineering (or equivalent) in EC/EE/CS with 5 or more years of experience in digital SoC development.
• Proficiency in RTL design using Verilog/SystemVerilog/VHDL for CPU/control sub-systems (AXI/AHB/APB bus) , SoC/ Subsystems (Ethernet/PCIE etc) and digital signal processing blocks (FIR filter, FFT, NCO).
• Experience with front-end tools such as Verilog simulators, linters, and clock-domain-crossing.
• Familiarity with gate-level simulation and LEC checking.
• Strong understanding of back-end design flow, including logic synthesis, constraints, timing analysis, and DFT.
• Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques.
• Excellent verbal and written communication skills, with the ability to effectively present technical information.

Desirable Skills:

• Experience in RTL coding and simulation using Verilog/SystemVerilog/VHDL.
• Familiarity with design simulation and checking using Cadence front-end tools such as Xcelium, SimVision, and Jasper RTL Apps.
• Proficiency in Python and Perl scripting for verification automation and report generation.