As a Senior Verification Engineer, you will play a key role in the verification of complex IP/SoC designs using SystemVerilog and Universal Verification Methodology (UVM). You will work closely with our design and architecture teams to develop comprehensive verification plans, create verification environments, and execute tests to ensure the functional correctness of our designs.

Responsibilities:

• Develop and maintain verification environments using SystemVerilog and UVM methodology.
• Write and debug testbenches, test sequences, and test cases to verify IP/SoC functionality.
• Create and execute test plans to meet project goals and deadlines.
• Collaborate with design and architecture teams to ensure proper integration of verification components.
• Analyze and debug simulation failures to identify and resolve issues.
• Develop and maintain verification infrastructure, including scripts, utilities, and automation tools.
• Mentor junior verification engineers and provide technical guidance as needed.

Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in IP/SoC verification using SystemVerilog and UVM.
• Strong understanding of digital design concepts and verification methodologies.
• Experience with scripting languages such as Perl, Python, or TCL.
• Familiarity with industry-standard EDA tools and simulators (e.g., Synopsys VCS, Cadence Incisive).
• Excellent problem-solving and debugging skills.
• Strong communication and interpersonal skills, with the ability to work effectively in a team environment.

Preferred Qualifications:

• Experience with verification of high-speed interfaces (e.g., PCIe, DDR, Ethernet).
• Knowledge of formal verification techniques (e.g., Formal Property Verification).
• Familiarity with hardware description languages such as Verilog or VHDL.